This invention relates to a data control device and in particular a data control device suited to control a data transfer in a FIFO (First in/First out) type memory.
A FIFO type memory comprises a plurality of sequentially connected memory elements extending from the input terminal toward the output terminal thereof. In the FIFO type memory the storage of input data is sequentially started from that memory element at the output side of the memory and, when data is delivered, a data transfer is started from that memory element at the output side of the memory. In this case, data stored in each memory element are sequentially transferred to an "data-empty" memory cell at the output side of the memory.
This type of memory is controlled in the following way. A first step is to obtain, in addition to a data representing a data storage state in a specified memory element, data representing the data storage states of those memory elements situated immediately before and after the specified memory element. Then, in order to effect a determination of whether data should be transferred to the next stage memory element or data should be received from the preceding stage memory element complicated gate circuits are required. Furthermore, an extra signal is required to indicate whether all the memory elements are ready for data storage or ready for data readout. Moreover, a data transfer control is difficult in a case where a different data transfer time is involved in transferring data from one memory element to the next stage memory element.